Physical Design Engineer - Embedded System

Execute all aspects of physical design implementation, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, extraction, and timing closure for complex server chip designs. - Drive and own timing closure, power optimization, and signal integrity analysis to meet stringent performance targets. - Perform and resolve physical verification checks, including DRC (Design Rule Checking) and LVS (Layout Versus Schematic) sign-off. - Collaborate closely with RTL designers, circuit designers, and other cross-functional teams to ensure seamless integration and optimal performance. - Develop and maintain scripts and methodologies for improving physical design efficiency and quality. - Participate in the evaluation and adoption of new physical design tools and flows. - Contribute to the continuous improvement of physical design methodologies and best practices. Required Skills & Experience: - 5 years of hands-on experience in Physical Design (RTL to GDSII) for complex integrated circuits. - Proven experience with server-grade chip designs is highly preferred. - Expertise in industry-standard EDA tools: Placement & Routing: Synopsys ICC2/Fusion Compiler, Cadence Innovus Timing Analysis: Synopsys PrimeTime Power Integrity: Ansys RedHawk (or equivalent) - Strong understanding of deep sub-micron process technologies and their impact on physical design. - Solid understanding of timing closure concepts, methodologies, and techniques. - Proven ability to optimize designs for power, performance, and area (PPA). - Experience with physical verification (DRC/LVS) and sign-off flows. - Excellent problem-solving and analytical skills. - Strong communication and interpersonal skills. Bonus Skills: - Proficiency in scripting languages such as Tcl, Perl, or Python for automation and flow development. - Experience with low-power design techniques. - Familiarity with formal verification flows. (ref:hirist.tech)

Location: bangalore, IN

Posted Date: 4/19/2025