Design Verification Engineer - UVM/System Verilog

Responsibilities : - Execute thorough verification of complex IP or subsystems, ensuring high-quality and robust designs. - Develop and implement comprehensive verification environments using SystemVerilog (SV) and the Universal Verification Methodology (UVM). - Create detailed test plans based on design specifications and verification goals. - Develop and deploy effective testbenches, incorporating assertions and coverage metrics to ensure thorough verification. - Achieve functional and code coverage targets through rigorous test execution and analysis. - Demonstrate strong experience in verifying Fabric, Network-on-Chip (NOC), or Interconnect blocks. - Apply knowledge of industry-standard protocols such as the AMBA suite (AXI/ACE), PCIe, CXL, interrupt handling mechanisms, and power management techniques in verification. - Debug and analyze simulation failures to identify root causes and collaborate with design teams for resolution. - Contribute to the improvement of verification methodologies and best practices. - Participate in technical reviews and provide valuable feedback on design and verification plans. - (Plus) Utilize experience or knowledge in coherent traffic verification. Required Skills & Experience : - 4 years of hands-on experience in Design Verification. - Extensive experience in executing IP verification or subsystem verification of complex blocks. - Strong proficiency in SystemVerilog (SV) and the Universal Verification Methodology (UVM). - Proven ability to develop effective assertions, testbenches, test plans, and coverage strategies. - Strong experience in verifying Fabric, Network-on-Chip (NOC), or Interconnect blocks. - Solid knowledge of protocols such as the AMBA suite (AXI/ACE), PCIe, CXL, interrupt handling, and power management. - Excellent problem-solving and debugging skills. - Strong communication and collaboration skills. - Ability to work independently and as part of1 a team. - Bonus Skills (Good to Have) : - Experience or knowledge of coherent traffic verification. - Experience with formal verification techniques. - Familiarity with scripting languages such as Python or Perl for automation. - Experience with industry-standard simulation tools. (ref:hirist.tech)

Location: bangalore, IN

Posted Date: 4/18/2025