Analog Layout Design Engineer - VLSI

Role Overview : We are seeking a skilled Analog Layout Design Engineer to design and optimize analog IC layouts. You will work closely with analog and mixed-signal design teams to create efficient, high-performance layouts for complex analog circuits, ensuring they meet electrical and physical design requirements. This role demands a strong understanding of layout techniques, design for manufacturability, and the ability to optimize the analog layout for power, area, and performance. Key Responsibilities : - Design and implement analog layouts for custom analog ICs, ensuring compliance with electrical and physical design specifications. - Work on a variety of analog components, such as amplifiers, voltage regulators, oscillators, filters, and ADCs/DACs. - Perform layout versus schematic (LVS) and design rule checks (DRC) to verify layout integrity and ensure it meets required standards. - Optimize the analog layout for power, area, and performance. - Ensure proper matching and symmetry for analog circuits. - Work closely with circuit designers to refine layout details, including transistor sizing, routing, and parasitic extraction. - Apply DFM principles to ensure that layouts are manufacturable and can be fabricated in volume with high yields. - Work with process technology specifications (e., CMOS, BiCMOS, SOI) to ensure layout design is compatible with the fabrication process. - Perform parasitic extraction of the layout (e, resistance, capacitance, inductance) and run simulations to evaluate the impact of parasitics on circuit performance. - Optimize layout to reduce parasitic effects that could negatively impact the circuit's electrical performance. - Collaborate with analog circuit designers to discuss layout requirements, perform design reviews, and ensure proper implementation of analog functions. - Communicate effectively with cross-functional teams (e., design, validation, manufacturing) to ensure smooth project execution. Required Qualifications : - Bachelor's or Master's degree in Electrical Engineering, VLSI Design, or a related field. - 3 years of experience in analog layout design for custom ICs, with a solid understanding of analog circuit design principles. - Proficiency in Cadence Virtuoso or similar layout tools for analog design and verification. - In-depth knowledge of design rule checks (DRC), layout versus schematic checks (LVS), and parasitic extraction. - Strong understanding of analog and mixed-signal IC design and the ability to work on a variety of analog blocks. - Experience with parasitic extraction tools and simulation environments (e., Spectre, HSPICE). - Solid understanding of the CMOS process and other advanced process technologies. - Strong analytical and problem-solving skills, with the ability to troubleshoot complex design issues. - Experience with high-speed analog design, RF, or power management ICs. - Familiarity with thermal and electromigration analysis for layout optimization. - Experience with Design for Manufacturability (DFM) and Design for Testability (DFT) concepts. - Understanding of advanced packaging techniques and their impact on analog layout. - Familiarity with foundry process design kits (PDKs) and technology files. - Exposure to mixed-signal layout, clock tree design, or power grid design. - Knowledge of additional tools such as Synopsys IC Compiler or Mentor Graphics tools for full-chip design (ref:hirist.tech)

Location: in, IN

Posted Date: 1/17/2025