Design Verification Engineer

Principal Verification Engineer – Oxford or Bristol I am seeking an experienced Principal Verification Engineer to join a publicly listed company designing industry leading ASIC, for customers ranging from start-ups to blue chip companies, in industries including automotive, medical, space and mobile technology. The Principal Verification Engineer will not only strengthen the team through technical expertise but also bring leadership and grow the verification business within the company. To be successful in this role you must have a good understanding of different methodologies, but particularly SystemVerilog and UVM. Faced with a new project, you will have the ability to quickly decipher the verification challenge and help define an effective and pragmatic verification strategy. Key qualifications 10 years’ experience in industry working on a variety of verification projects. Extensive knowledge of verification methodologies particularly UVM and SystemVerilog. Strong experience in the specification and implementation of verification infrastructures, test benches, models, assertions, and functional tests in Verilog and SystemVerilog. Familiarity with constrained random verification methodologies, code coverage analysis and running regression tests. Strong VHDL/Verilog RTL. Very good understanding of modern verification flows and methodologies and able to influence the company towards continuous improvement. A good understanding of functional safety and quality processes, to achieve ISO26262 or similar will be considered as a strong plus. On offer is a salary up to £95,000 (experience dependent) plus a bonus and company share options scheme. You must be happy to go onsite weekly. You must have UK working rights. For more information on this great opportunity please contact Rachel Mason at IC Resources.

Location: Oxford, GB

Posted Date: 1/15/2025