Physical Design Engineer

Develop and maintain synthesis constraints at the module and full-chip level. Promote module-level SDC to full-chip level SDC. Utilize industry-standard synthesis tools to optimize designs for performance, power, and area. Collaborate with RTL design teams to create accurate and efficient constraints. Execute synthesis runs and analyze synthesis reports to identify and resolve issues. Handover optimized netlists to the physical design team.

Location: Santa Clara, CA, US

Posted Date: 1/12/2025