Static Timing Analysis Engineer

About the Role : LeadSoc Technologies is seeking a highly skilled Senior STA Engineer to join our dynamic team in Bangalore. In this role, you will play a critical role in ensuring the timing integrity of complex SoCs. You will be responsible for performing advanced static timing analysis, generating ECOs, and collaborating with design teams to achieve optimal timing closure. Key Responsibilities : - Constraint Development : Develop and maintain accurate and robust timing constraints for both functional and test modes. - Static Timing Analysis : Perform in-depth static timing analysis (STA) at the block and top-level to identify and resolve timing violations. - ECO Generation : Generate and implement ECOs to fix timing violations, working closely with design teams to minimize design impact. - Power Analysis : Analyze power consumption and identify optimization opportunities. - Automation : Develop and maintain scripts to automate routine tasks and improve efficiency. - Collaboration : Work closely with design, physical design, and verification teams to ensure timely and high-quality deliverables. Required Skills and Experience : - Strong understanding of static timing analysis concepts and methodologies. - Proficiency in industry-standard STA tools (e., Synopsys PrimeTime, Cadence Tempus). - Experience in handling complex timing constraints and ECO generation. - Strong scripting skills (Perl, Tcl, Python) for automation. - Experience with advanced node technologies (3nm, 5nm) is highly preferred. - Excellent problem-solving and analytical skills. - Strong communication and teamwork abilities. Preferred Qualifications : - Experience with formal verification tools and techniques. - Knowledge of low-power design techniques (ref:hirist.tech)

Location: bangalore, IN

Posted Date: 1/12/2025