Senior Design Verification Engineer - System Verilog

bout the Role : We are seeking a highly skilled and experienced Senior Design Verification Lead to join our team. In this role, you will be responsible for leading and executing complex design verification tasks at the IP and subsystem level. You will be working independently on critical projects, requiring a strong technical foundation and problem-solving abilities. Key Responsibilities : - Design Verification : Develop and execute comprehensive verification plans and testbenches using SystemVerilog (SV) and Universal Verification Methodology (UVM). - Testcase Development : Create and maintain high-quality testcases to thoroughly validate design functionality and performance. - Debugging and Analysis : Conduct in-depth debugging of test failures, identify root causes, and propose effective solutions. - Technical Leadership : Provide technical guidance and mentorship to team members, fostering a collaborative and innovative work environment. - Collaboration : Work closely with design engineers to understand design specifications and ensure seamless integration of verification efforts. Required Skills and Experience : - Strong proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM). - Hands-on experience in developing complex verification environments, including testbench components, testcases, and assertions. - In-depth understanding of digital design concepts and verification methodologies. - Proven ability to independently debug and analyze complex issues. - Strong knowledge of industry standard protocols like PCIe and AXI. - Excellent problem-solving, analytical, and communication skills. - Ability to work independently and as part of a team. - Preferred Qualifications: Experience in leading and mentoring verification teams. - Knowledge of scripting languages (Perl, Python, etc.) for automation. - Familiarity with formal verification techniques (ref:hirist.tech)

Location: bangalore, IN

Posted Date: 1/12/2025