VLSI Engineer - SoC

Company : Leading MNC Location : Pan India Experience : 5yrs ASIC/SoC RTL : - Expertise in SoC subsystem/IP design - Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog - In depth knowledge on RTL quality checks (Lint, CDC) - Knowledge of synthesis and low power is a plus - Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) - Good understanding of timing concepts - Expertise in setting up and using tools Physical Design : - In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification. - Should have experience on programming in Tcl/Tk/Perl. Design Verification : - Experience in IP/Subsystem level Verification - Good hands-on experience in verifying PCIe protocol (Gen4/Gen5/Gen6) - Good knowledge on PCIe transaction layer, routing, reset flows etc Analog Circuit Design : - Should have hands on experience in designing critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap ckts - Experience in designing Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. - Experience in dealing the challenges in lower technology nodes w.r.t. specifications Analog Layout Design : - Good hands on experience in lower technology nodes like N3, N5 - Working knowledge on DDR and SERDES kind of Ips - Ability to lead few junior engineers for the successful execution - Good tool knowledge on Cadence XL and Calibre verification Emulation : - A good understanding of architectural aspects and RTL code at IP/Sub-system/SoC level - A good understanding of verification methodologies including SV-UVM/C based environment, transactors etc - Knowledge of Arm CPU cores, protocols including PCIe, USB, Ethernet, AMBA, UART/SPI/I2C, DDR, flash memories and their usage in SoC environments is necessary FPGA Prototyping TVC:- - Good understanding of verification and validation fundamentals - Solid understanding of FPGA platforms like HAPS, proFPGA etc - Good understanding of ARM based IPs, subsystem and SOC - Integrate daughter cards and bring them up with real world devices and testers - Knowledge of this protocols will be plus, I2C, I3C, SPI, SPMI, USB, PCIe DFT : - Implementation tools like Mentor Tessent Fastscan, Testkompress or Synopsys DFT compiler and Tetramax - Sound knowledge of ATPG/Scan, coverage analysis, EDT compression - Exposure to Static timing in DFT modes to debug constraint issues and review/analyze timing reports. (ref:hirist.tech)

Location: in, IN

Posted Date: 11/26/2024