Physical Verification Lead - EDA

Physical Verification Lead Experience - 10 years Location - Bangalore Notice Period - immediate to 15 days - Typically requires more than 10 years of relevant industry experience. - Hands on experience into Physical verification at block-level & chip-level. - Hands on debugging skills in different physical verification checks like LVS,DRC,ERC,PERC, Antenna, ESD and DFM using Mentor Calibre, ICV and Pegasus PV Synopsys ICV, etc. - Hands on experience to Physical Verification Process - Experience in leading PnR execution at subsystem level, IP blocks like Serdes - Experience in ECO implementation preferred - Experience in both Synopsys and Cadence based tools - Expertise in Static timing analysis, Floor Planning, Power Planning and Placement - Hands on debugging skills in different physical verification checks like LVS,DRC,ERC,PERC, Qrc, IR: Voltus, Antenna, Sta: PrimeTime, Tempus Power: PTPX ESD and DFM using Calibre, ICV and Pegasus PV tools - Expert in Verilog, Python, Tcl, C, shell script, PnR: FC, ICC2, Innovus - Expertise in Clock tree synthesis, Routing - Expertise in Physical verification lvs, drc. - Experience in custom cell lib characterization, macro lib characterization - Experience in various technologies - 5nm, 7nm, 10nm, 14nm, 16nm, 28nm, 40nm, 55nm,90nm - Experience in flow and automation development for in-house productivity acceleration - Experience in EDA tool development - Must have good communication & problem-solving skills. - Should be able to handle PnR tasks with minimal supervision advantage (ref:hirist.tech)

Location: bangalore, IN

Posted Date: 11/25/2024