Formal Verification Engineer - Hardware Design

Formal Verification - Create Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics. - Implementation and maintenance of Formal Verification environments in Chisel - Applying various FV techniques to reduce complexity and prove correctness of DUT. - Debugging RTL to identify causes of failure scenarios. - Guide and train team members on effective usage of Formal Verification tools - Develop/modify scripts to automate the verification process. - Review formal setups and proofs with design and verification teams. - Maintain and extend assertion libraries. - 7 years of experience in Formal Verification of Digital Hardware Design - Extensive experience with Formal Abstraction Techniques and sign-off process - Familiarity with industry-standard Formal Verification Tools, such as VC Formal, Jasper Gold - Knowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ System Verilog (ref:hirist.tech)

Location: hyderabad, IN

Posted Date: 11/25/2024