Static Timing Analysis Lead - Synopsys/EDA

About the Role : Leadsoc Technologies is seeking a highly skilled Senior Static Timing Analysis (STA) Engineer to join our team. As a Senior STA Engineer, you will play a critical role in ensuring the timing closure of complex SoC designs. You will be responsible for optimizing design performance, identifying and resolving timing issues, and collaborating with cross-functional teams to deliver high-quality products. Experience : 8 years of relevant experience. Expectations : - Candidate should have strong STA fundamentals. - Has done timing sign-off including timing margin calculations independently on SoC level. - Experience in handling STA of multi-power domain designs. - STA flow enhancement, abstraction with bottleneck identification. - Proficient in design margins and SDC constructs. - TAT reduction in multi-mode, multi power domain/designs. - Generate timing ECOs for Physical design. - Drive ambitious schedules and enables dependent teams to accomplish. - Proficient with EDA tools from Synopsys/Cadence. - Excellent analytical & communication skills. - Show ability to collaborate in a multi-functional environment, cross-site or cross-time zone. - Proficient in Tcl and Perl or other scripting relevant language is a plus. Key Responsibilities : - Perform advanced static timing analysis (STA) using industry-standard tools (Synopsys/Cadence). Analyze and optimize design performance to meet timing closure targets. - Identify and resolve timing violations through clock gating, power gating, and other optimization techniques. - Develop and implement STA methodologies to improve efficiency and accuracy. - Generate timing reports and summaries for design reviews and sign-offs. - Collaborate with design, verification, and physical design teams to address timing issues. Drive and maintain efficient STA workflows, including bottleneck identification and improvement. - Develop timing constraints (SDC) and ensure proper margin incorporation. - Manage timing budgets and ensure timely completion of deliverables. - Generate timing ECOs for physical design. - Proactively identify and suggest improvements to the STA flow. - Stay up-to-date with the latest STA tools and methodologies. Required Skills and Experience : - 8 years of experience in Static Timing Analysis (STA) of complex SoC designs. - Strong understanding of timing analysis fundamentals, including clock tree analysis, path analysis, and slack analysis. - Expertise in using industry-standard STA tools (Synopsys PrimeTime, Cadence Tempus). - Experience with multi-power domain designs and timing analysis techniques. - Proficiency in design margins and SDC constructs. - Proven ability to reduce TAT (Turn Around Time) for STA in multi-mode, multi-power domain designs. Excellent analytical and problem-solving skills. - Strong communication and collaboration skills. Ability to work independently and as part of a team in a fast-paced environment. Preferred Skills : Experience with low-power design techniques. Knowledge of scripting languages (Tcl, Perl) for automation and customization of STA flows. Experience with formal verification (ref:hirist.tech)

Location: bangalore, IN

Posted Date: 11/24/2024