Principal IC DFT Engineer

Raspberry Pi is seeking an experienced DFT specialist engineer to join our innovative team. The role is based on-site in Cambridge with an expectation that the successful candidate comes into the office a minimum of 3 days per week. The work of the ASIC team includes:

• Architecture, tradeoffs with software/hardware
• RTL design
• IP selection and integration
• Verification at block and system level
• FPGA platforms for software development and extended verification
• Implementation including DFT, Synthesis, Place and Route, Timing closure and Signoff checks
• Package definition and working with assembly partners
• Validation and characterisation
• Test pattern generation and ATE bring-up
• Production monitoring and management

Requirements

You would be involved in hands-on DFT implementation and verification across a variety of current silicon technologies. You would be responsible for the design, development, and implementation of IC DFT test solutions, liaising across various groups and functions. You would be involved with the architecture and development of test methodologies, ensuring adequate inclusion of test structures to enable fully and efficiently testable devices, including the following:

• Hierarchical DFT (EDT flows)
• On-chip clocking structures
• ATPG compression, serialisation, and multiplexing
• Guide scan insertion providing input to Synthesis scripts
• Review, assess, and correct DFT DRC warnings
• Create STA DFT mode constraints, review failing paths, create exception list for ATPG
• Simulation (behavioural and gate-level)
• RTL design of test structures
• BIST (Memory/Logic/IP)

Job requirements:

• Willingness to contribute and share activities with a wider team
• Strong grounding in IC development flows
• Hands-on current experience with modern DFT tools
• Good understanding of partitioning and on-chip clocking
• Experience in ATPG and simulation debug

The following would also be useful:

• Experience with either Cadence or Mentor DFT tools preferred
• Understanding of silicon technologies, finFET, and fault models
• Logic BIST implementation, full or as part of an ATPG flow
• Familiarity with test access standards, e.g. IEEE1687